In recent years, a system LSI (such as an ASIC (Application Specific Integrated Circuit), and an FPGA (Field-Programmable Gate Array)) which integrates, on a single semiconductor, a logic circuit, a CPU, and a program memory storing a program of the CPU has been actively developed.
A system LSI is a core portion of an electronic device in which the system LSI is assembled, and a technique of disassembling and analyzing the system LSI is progressing.
However, in recent years, such progress of an analysis technique of a system LSI has been abused and a system of dead-copying (imitating) the circuit of a system LSI is often seen. To prevent such an imitation of a system LSI, an FPGA technique for preventing an analysis and a dead copy of a system LSI has been proposed (for example, refer to Japanese Patent No. 4,191,170).
In the FPGA technique, a system LSI is provided with the FPGA, a ROM (Read Only Memory) storing user circuit data and a start key code string, and a gate array exclusive for a user in which a start key information is assembled in advance. The gate array exclusive for a user boots the FPGA by data of a user circuit in the case that the information derived from the start key code string matches the start key information. Accordingly, in the system LSI, a person holding a gate array exclusive for users provided with a correct start key information is allowed to perform the operation of the system, but a person not holding a gate array exclusive for users provided with a correct start key information is prohibited from performing the operation.
In the FPGA technique, however, to prevent a dead copy by analyzing the system LSI, a dedicated gate array has to be prepared in addition to the FPGA, and there is a problem that a manufacturing cost increases.
When the dedicated gate array is imitated by analyzing the inside of the dedicated gate array, there is a problem that the system LSI itself is dead-copied.